[kawamaster]

Superscalar describes a microprocessor design that makes it possible for more than one instruction at a time to be executed during a single clock cycle. In a superscalar design, the processor or the instruction compiler is able to determine whether an instruction can be carried out independently of other sequential instructions, or whether it has a dependency on another instruction and must be executed in sequence with it.
The processor then uses multiple execution units to simultaneously carry out two or more independent instructions at a time. Superscalar design is sometimes called "second generation RISC.
Is this the case with the G5?

[mgbasinski]

If you go look at the material on the Apple web page about the G5 processor, you can find all the detail you want on the G5 processor. In particular, there is a G5 processor whitepaper, which contains loads of detailed info, starting with a list of key features including the statement:
"Superscalar execution core supporting up to 215 in-flight instructions"
Mark